module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n  ); 
    
    wire e;
    assign e=a&b;
    wire f;
    assign f=c&d;
    wire g;
    assign g=e|f;
    assign out=g;
    assign out_n=~g;

endmodule